High speed design requires careful consideration of the PCB stack-up, layer usage, trace width, vias and stubs, return currents, potential cross talk, and terminations.
High speed signals might be specified by their data rate or rise time. Recent designs include:
- over 16Gbps for Xilinx GTH transceivers
- 120pS typical rise time for LVPECL
- 40pS rise CML transceivers
- 12pS rise time from an HMC841LC4B D-FF
High speed PCB designs use controlled impedance traces. The trace widths all depend on the dielectric material, thickness, and type of transmission line implemented.
- Microstrip – surface traces referenced to an internal layer. For wider traces in select areas, a deeper reference layer can be used with copper keep outs in the intermediate layers.
- Stripline – typically a trace sandwiched between two ground planes.
- Asymmetric Stripline – a stripline with two different dielectric thicknesses to the reference planes. The asymmetry can be due to slightly different core and prepreg dielectric thickness or by using two signal layers between two planes.
- Differential pairs – edge coupled microstrips or striplines used for LVDS, CML, LVPECL, Diff HSTL, or other differential pair signals. Traces within the pair are only loosely coupled, with the reference plane as the primary return path.
- CPWG – Co-Planar Waveguide with Ground – a microstrip with surface ground coupled on either side of the trace.
Some applications, like PCIe and DIMM’s, specify the PCB thickness which can limit the number of layers or force thin dielectric layers to be used. Thinner dielectrics require thinner traces to meet the control impedance requirements. Traces as small as 3mils can be required, but most designs do not use traces smaller than 4 to 5 mils.
Like traces, PCB vias are available in a variety of forms:
- Laser or stacked laser vias – blind vias from the outer layer to layer 2, 3 or 4.
- Signal Integrity or SI Vias – ground vias placed near signal vias to allow return currents to change layers.
- Thermal vias – vias typically located in a exposed ground pad of an IC to conduct heat from the IC through the PCB to improve heat dissipation.
- Back drilled vias – When a blind laser via cannot extend deeply enough into the PCB, back drilling to remove the via stub may be required. Only used as a last resort.
- Filled vias – vias are filled with epoxy, typically non-conductive to match CTE. Filled vias may be used to prevent solder wicking or prevent airflow through the vias.
- Via in pad – filled vias, machined flat, and plated to provide a solder pad, used in a dense PCB’s or fine pitch BGA’s.
- Tenting vs non-tented – Is the via covered with solder mask?
Typical dielectric materials:
- FR408HR (lower Dk, lower loss)
- Nelco 4000-13, (SI for lower Dk glass, EP for higher temp)
Advanced dielectric materials:
- Panasonic Megtron6 – low loss, high speed (Df 0.004 @ 10GHz)
- Rogers RO3003 – PTFE microwave
- Dupont KX 04J – 1.0mil polyimide, Dk = 3.5, 0.8nF/in2
- 3M C1012 – 0.5mil thick ceramic, Dk=22, 10nF/in2
- Cadence Concept (schematic capture) and Allegro (PCB design)
- Altium (schematic capture and PCB design)
- Orcad (schematic capture)
- DxDesigner (schematic capture) and PADS (PCB design)
- HyperLynx (Signal Integrity)