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The design was routed on 18 layers, which is far from my highest layer count ever, but the part density required filling both sides of the PCB. Because the design filled both sides of the PCB, stacked laser vias from 1-3 and 16-18 and buried vias from 2-9, 10-17, and 2-17 were required. Offset laser vias from 1-2 or 17-18 were used when connecting a buried via to an outer layer. The DDR3L used clam shell routing, with some memories on both sides, buried/blind vias in each half, and one set of through vias between the 2nd and 3rd memory IC’s to pass the address and control from the top layers to the bottom set of layers. Because the buried vias were less then half the length of the board thickness, those vias could be slightly smaller in diameter, which helped with clearances in 0.8mm pitch DRAM, and kept the stubs on the signals shorter, which helped with the SI on the fly-by routing. The flash and the large connectors overlapped on opposite sides of the PCB. The 16Gbps serdes added a requirement that stubs on those signals be very short, so serdes pairs were restricted to layers 1, 3, 16, and 18. Power rails also competed for copper area. I spent a lot of time planning placement, layer usage, using Hyperlynx for SI, and working with our best layout designer. He did an excellent job and final design was a work of art.
For testing, I made a custom 10”x 15” test board that had connectors for all of the I/O, over 150 SMA, DSUB’s, headers, power supplies, oscillators, A/D converters, and 2 more Gigabit Ethernet PHY’s. Loopback cables were used to test most of the I/O. Most of the problems during prototype testing came from Vivado issues with the new Ultrascale+ components. Version 2016.3, then 2016.4, of the software cleared up most of those. The boards themselves functioned very well and the design has now entered its first production run.